1. Field Of The Invention
The present invention relates generally to filtering signal noise in integrated circuits, and more particularly to a decoupling capacitor multiplier circuit.
2. Description Of The Background Art
Integrated circuits (hereafter xe2x80x9cICsxe2x80x9d) may be typically designed as direct current (DC) circuits. The component devices constituting the IC operate within predetermined voltage thresholds, and therefore may fail when random electrical fluctuations cause operating thresholds to be exceeded. IC circuits are subject to numerous sources of random electrical fluctuations, including fluctuations caused by switching devices and naturally occurring noise from a DC power source. For practical purposes, the aforementioned electrical fluctuations are functionally equivalent to alternating currents (AC), and are hereafter referred to as the AC components in the DC signals.
As a result of the potential for device failure caused by excessive AC components in the DC signals, decoupling capacitors are typically used to filter out or dampen the AC components. FIG. 1A schematically illustrates a common use of the decoupling capacitor for filtering AC components from an input signal Vd 2. In FIG. 1A, passive decoupling capacitor 6 is connected directly to the input signal Vd 2 and to the ground (VGND) 8. This simple connection allows the AC component of the input signal Vd 2 to pass through to ground 6. A frequency domain analysis of FIG. 1A yields an admittance of: id/vd=sCd. As is evident from the frequency domain analysis, the admittance as seen by input signal Vd is proportional to the capacitance of decoupling capacitor Cd.
In operation, the decoupling capacitor Cd 6 acts like a reserve of current smoothing out the xe2x80x9cdipsxe2x80x9d and xe2x80x9cpeaksxe2x80x9d in the DC input signal Vd 2. The charged decoupling capacitor Cd 6 helps to fill in any dips in the input signal Vd voltage by releasing its charge when the voltage drops, or by storing charge when the voltage peaks. The size of the decoupling capacitor Cd 6 determines how big of a dip it can fill, or how big of a peak it can smooth out. The larger the decoupling capacitor 6, the larger the dip and peaks it can handle. Large loads delivered by power sources often require a very large capacitance for effective decoupling.
FIG. 1B schematically illustrates a conventional decoupling scheme for a power source. In practice, because a power source may require a large capacitance for proper decoupling, the required capacitance is often achieved by using a number of smaller capacitors 10N connected in parallel. Typically only a portion of the required decoupling capacitors are integrated on the chip die because they require too much costly chip die real estate. Accordingly, in some cases, the decoupling capacitors are implemented as separate components from the IC and connected to the IC via the printed circuit board (xe2x80x9cPCBxe2x80x9d). A drawback to this technique, however, is the added PCB space required to accommodate the decoupling capacitors, and therefore the added increase to the overall size of the electronic device.
A decoupling circuit comprising a first capacitor, and a first current mirror coupled to the capacitor, wherein the first current mirror is configured to multiply the capacitance effect of the first capacitor is disclosed. The first current mirror may comprise a first transistor and a second transistor coupled to the first transistor. The first transistor and the second transistor may comprise n-channel MOSFET transistors. The decoupling circuit may further comprise, a bias network coupled to the first current mirror, wherein the bias network is configured to bias the first current mirror. The bias network may comprise a p-channel MOSFET.
In another aspect of the invention, the decoupling circuit additionally comprises a second capacitor, and a second current mirror coupled to the capacitor, wherein the second current mirror is configured to multiply the capacitance effect of the second capacitor. An input node may be connected to the first current mirror and the first capacitor, and the second current mirror and the second capacitor, wherein the input node is configured to receive an input signal in a first polarity and a second polarity opposite to the first polarity. Depending on the polarity of the input signal, the input signal is decoupled by either the first current mirror and the first capacitor, or the second current mirror and the second capacitor.
These and other features and advantages of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.